1. Field of the Invention
The present invention relates to an optical media disc driver circuit and in particular, an optical driver circuit having a multiphase clock generator including a delay locked loop (DLL) circuit.
2. Description of the Related Art
DVD±R discs, which record data once, store data by using changes in the reflectivity of a photosensitive material on the disc. The system shines a tightly focused, relatively high-power, 650-nanometer (nm) red laser beam onto the surface of the DVD. The light causes a permanent change in the reflectivity of the disc's surface. Information can then be recovered by illuminating the disc's surface with a lower-powered laser light. A detector receives the reflected laser light, and the system uses the varying reflectivity to re-create the original data with great integrity. DVD±RW discs utilize temperature-induced phase changes in a very thin metal alloy layer deposited on the surface of the disc. The material is designed to have two stable, solid states. The disc can store data because these states have different reflectivity characteristics. The system recovers data in the same way as for a write-once disc.
Driving circuits for writing to optical storage media such as a Compact Disc Player (CDP), a Digital Video Disc Player (DVDP), a CD-RW (Rewritable Compact Disc), a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable compact disc), a DVD-RAM, or a DVD-ROM etc. generally use a PLL (phase locked loop) circuit or a DLL (delay locked loop) circuit for generating a number of clock signals (hereinafter referred to as “multiphase clocks”) for data modulation/demodulation and for synchronizing/serializing data at high speed.
A phase-lock-loop or a delay-locked-loop (PLL) circuit is usually used as a multiphase clock generator for generating multiphase clock signals. A PLL circuit uses a voltage controller and a phase comparator. Similarly, a DLL (delay locked loop) circuit uses delay cells and a phase comparator circuit to generate the multiphase clock signals. Generally, a circuit including a DLL has better jitter characteristics than a circuit including a PLL.
With increasing demand for higher optical disc burning (and reading) speeds, it has been difficult to meet the need for high-speed delay-locked loops (DLLs). For example, it is not easy to increase the frequency of voltage-controlled delays (non-inverting buffers) included in a DLL to a high frequency approaching or above a GHz level (because propagation delay of such delay cells produced is constrained by the manufacturing process).
When serial data are transmitted or received at high speed, multiphase clock signals are needed. The multiphase clock signals generated are synchronized to the input clock (sync) signals. Each of the multiphase clock signals has a phase difference (relative to the input clock (sync) signals) and the same interval (period) as between input clock (sync) signals.
FIG. 1 is a circuit block diagram illustrating a conventional starved-current (voltage controlled) inverter type DLL (delay locked loop) used as a multiphase clock generator. The conventional DLL of FIG. 1 generates and outputs a number M of multiphase clocks (e.g., for sampling a character (M=32 symbol bits) in the receiver circuit) synchronized to a 800 MHz frequency. The receiver requires 32 phase clock signals. Operating from an input clock at 800 MHz, the 32 phase clocks operate at 32×800 MHz or at 25.6 Gbits/sec. Therefore, one “step” delay (between successive multiphase clocks) is 39.06 psec (1/(32×800 [MHz])=39.06 [psec]).
A starved-current (voltage controlled) inverter type DLL uses delay cells which typically have a propagation delay (“Low-to-High” or “High-to-Low”) of less than 50 psec. To decrease the delay at each cell, the total power consumption of the delay locked loop circuit is increased and circuit size may be increased. Therefore, the conventional delay locked loop circuit is inappropriate for an optical driving system requiring high frequency operation at 800 MHz or more (e.g., gigahertz frequencies).
The conventional DLL (delay locked loop) circuit of FIG. 1 has a delay chain (11), a phase detector (13), a charge pump (15) and a loop filter (17). The delay chain (11) includes a plurality M of delay cells (111, 112, 113, . . . 11M) that each delays an input clock signal (CLKIN) in response to a control voltage (VCON). Each of the delay cells(111 to 11M) respectively has a delay time(Δ) corresponding to T/M (where T is the period of the input clock signal(CLKIN). For example, if the frequency (f) of an input clock signal (CLKIN) is 800 MHz and the number of delay cells (111-11M) is 32 (i.e., M=32), the delay time (Δ) of each of the delay cells (111-11M) is 39.06 picoseconds (1/(f×M)=1/(800×106×32)=39.06×10−12 sec).
FIG. 2 is a timing diagram illustrating plural clock signals generated from the DLL (delay locked loop) circuit of FIG. 1. The clock signals (CLK<1> to CLK<M>) have M (where M is an integer greater than one) different phases respectively, are output from the plurality M of delay cells (111to 11M) respectively.
Referring to FIG. 1, the phase detector (13) generates an UP signal or a DOWN signal corresponding to a detected phase difference between output clock signals. The charge pump (15) sources or sinks a prescribed current to an output unit. The loop filter (17) generates a control voltage (VCON) by filtering the charge pump (15) output.
Hence, if a current supplied to the delay cells (111 to 11M) is increased, the delay time (Δ) of each of the delay cells is decreased. Conversely, if the current supplied to the delay cells (111 to 11M) is decreased, the delay time (Δ) of each of the delay cells is increased. Accordingly, the DLL (delay locked loop) circuit primarily uses a starved-current inverter type as the delay cells (111-11M). It is difficult to make a delay cell having less than a 50 picosecond delay time because a propagation delay time is about 50 picoseconds with the general semiconductor manufacturing process. The total power consumption in the DLL (delay locked loop) circuit is increased when “inner current” supplied to the delay cells is largely increased.
Therefore, the conventional DLL (delay locked loop) circuit is inappropriate for use as a multiphase clock generator in an optical driving system requiring high frequency operation at of 800 MHz or more.
A laser diode is used for “writing” data to an optical disc (e.g., a CD-R or a DVD-RW) and the laser diode power (LDP) signal (current) is alternated between a low level (space: logic 0) and a high level (mark: logic 1). Laser diode drivers (LDDs) are electrical-based devices that convert voltage into current, which the laser diode then converts into a light pulse to burn information onto an optical disc. The “high” (“write”, “full”) power level of the laser diode power signal (LDP) creates a “mark”, and the “low”(“erase”) level creates a “space” on the optical disc. Unfortunately, the resolution of a CD player's optics is not sufficient to read directly a sequence of 1s or 0s following each other too closely, i.e. 111111. Another limitation is the maximum length of a given mark or space (pit or land), in order to leave room for the clock (synchronization) data. Therefore, it was agreed to keep at least two 0s between two 1s and, that the maximum length of marks (pits) was limited to 10 bits in a row. Because of how the laser of a CD-player detects ones and zeroes on the CD, there cannot be consecutive ones when storing the digital information. The solution for this problem is called eight-to-fourteen modulation (EFM). In the eight-to-fourteen conversion system each 8 user-bit byte is converted into a 14 channel-bit modulation code (EFM code). Thus, eight bit chunks of information are transformed to fourteen “channel” bits. Also, three merging bits of zeros are tacked on to each fourteen bit chunk.
EFM code marks and spaces are written on an optical media in nine different lengths, from T3 (1001) to T11 (100000000001). T for a “4×DVD” system is 9.56 nsec. The laser diode power (LDP) signal is modulated ON/OFF (e.g., as EFM code) that is to be written to the optical media by the laser diode. The first CD drives played back 75 blocks per second (176400 channel bits per second), which translated into the data transfer rate “1×” equal to about 0.15 MB/s.
FIG. 15 is a timing diagram of laser diode power (LDP) showing widening data grooves in a conventional optical driving system. In the case where the laser diode power (LDP) signal is held “ON” constantly at the fixed high level (e.g., a T11 mark: logic 1), the data groove width written to the optical disc can increase from a proper narrow width to an improper wide width. This is generally due to “thermal creep”.
If the LD power (current through the laser diode) is held at a constant (fixed) high level, such as while writing a long “mark” (e.g., T11), a groove width written to the optical disc is increased to a wide width. Accordingly, the mark written in one data groove can become overlapped with data in an adjacent data groove, causing a data read error because adjacent data grooves are overlapping.